1. Field of the Invention
The present invention relates to a solid-state image pickup device and an image pickup device in which a plurality of substrates where circuit elements forming pixels are disposed are electrically connected to each other. In addition, the present invention relates to a signal reading method of reading a signal from a pixel.
Priority is claimed on Japanese Patent Applications No. 2011-263578, filed Dec. 1, 2011, No. 2012-112537, filed May 16, 2012, and No. 2012-178332, filed Aug. 10, 2012, the contents of which are incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
In recent years, with rapid spread of personal computers, demands for digital cameras which are image input apparatuses have been enlarged. There are several factors determining image quality of a digital camera, and, among the factors, the number of pixels of an image capturing element is the greatest factor determining the resolution of a captured image. For this reason, a digital camera with twelve million or more pixels has been recently commercialized.
There is known an amplification type solid-state image pickup device represented by a MOS type image sensor using a CMOS (Complementary Metal Oxide Semiconductor) as an image capturing element, or a charge transfer type solid-state image pickup device represented by a CCD (Charge Coupled Device) image sensor. These solid-state image pickup devices are widely used in digital still cameras, digital video cameras, and the like. Recently, as a solid-state image pickup device mounted in a mobile apparatus such as a mobile phone with a camera or a PDA (Personal Digital Assistant), a MOS type solid-state image pickup device having a low power supply voltage has frequently been used from the viewpoint of power consumption and the like.
In the related art, in the MOS type solid-state image pickup device, various solid-state image pickup devices have been proposed in which a semiconductor chip where a pixel region in which a plurality of pixels are arranged is formed and a semiconductor chip where a signal processing circuit is formed are electrically connected to each other so as to constitute a single device. For example, Japanese Unexamined Patent Application, First Publication No. 2006-49361 discloses a solid-state image pickup device in which a semiconductor chip where a micro pad is formed for each unit pixel cell or each cell collecting a plurality of pixels on a wire layer side and a signal processing chip where a micro pad is formed on a wire layer side of a position corresponding to the micro pad of the semiconductor chip are connected to each other using a micro bump.
FIG. 12 shows a configuration of a solid-state image pickup device in the related art. The solid-state image pickup device in the related art is formed by vertically overlapping a first substrate 201 having a MOS type image sensor with a second substrate 202 having a signal processing circuit. In the first substrate 201, light is incident from a surface on an opposite side to a surface connected to the second substrate 202. That is to say, in the first substrate 201, a wire layer is formed on the front surface side of the substrate, and light is incident from the rear surface side opposite to the front surface where the wire layer is formed.
In the wire layer of the first substrate 201, as described later, a plurality of micro pads 203 are formed for each cell including unit pixels, or for each cell collecting a plurality of pixels. In addition, a plurality of micro pads 204 corresponding to the micro pads 203 of the first substrate 201 are formed on the surface of a wire layer side of the second substrate 202. The first substrate 201 and the second substrate 202 are disposed in an overlapping manner such that the micro pads 203 and the micro pads 204 face each other. The micro pads 203 and the micro pads 204 are electrically connected to each other via micro bumps 205 and thereby are integrally formed. The micro pads 203 and 204 are formed using micro pads smaller than typical pads.
The second substrate 202 is formed so as to have an area larger than that of the first substrate 201. On the front surface of the second substrate 202, typical pads 206 are disposed at positions corresponding to the outside of the first substrate 201. The pads 206 constitute interfaces with systems other than a system including the two substrates.
FIG. 13 shows a configuration of the first substrate 201. The first substrate 201 includes a pixel unit 208 where a plurality of pixel cells 207 are arranged two-dimensionally, and a control circuit 209 which controls the pixel cells 207.
FIG. 14 shows a circuit configuration in the pixel cell 207 of the first substrate 201. Here, four pixels form a single pixel cell. The pixel cell 207 includes four photoelectric conversion elements 221A, 221B, 221C and 221D. The photoelectric conversion elements 221A, 221B, 221C and 221D are respectively connected to sources of corresponding four transfer transistors 222A, 222B, 222C and 222D. Gates of the transfer transistors 222A, 222B, 222C and 222D are respectively connected to transfer lines 227A, 227B, 227C and 227D via which transfer pulses are supplied. Drains of the transfer transistors 222A, 222B, 222C and 222D are commonly connected to a source of a reset transistor 223. A charge storage unit FD which is called a floating diffusion located between the drains of the transfer transistors 222A, 222B, 222C and 222D and the source of the reset transistor 223 is connected to a gate of an amplification transistor 224.
A drain of the reset transistor 223 is connected to a power supply line 232, and a gate of the reset transistor 223 is connected to a reset line 228 via which a reset pulse is supplied. A drain of an activation transistor 225 is connected to the power supply line 232, and a source of the activation transistor 225 is connected to a drain of the amplification transistor 224. A gate of the activation transistor 225 is connected to an activation line 229 via which an activation pulse is supplied. A source of the amplification transistor 224 is connected to a drain of an injection transistor 230. A source of the injection transistor 230 is connected to a ground potential, and a gate of the injection transistor 230 is connected to an injection line 231 via which an injection pulse is supplied. A connection midpoint between the amplification transistor 224 and the injection transistor 230 is connected to an output terminal 226.
The photoelectric conversion elements 221A, 221B, 221C and 221D, which are, for example, photodiodes, generate signal charges based on incident light, and store and accumulate the generated signal charges. The transfer transistors 222A, 222B, 222C and 222D are transistors which transfer the signal charges accumulated in the photoelectric conversion elements 221A, 221B, 221C and 221D to the charge storage unit FD. Turning-on and turning-off of the transfer transistors 222A, 222B, 222C and 222D are controlled by transfer pulses supplied from the control circuit 209 via the transfer lines 227A, 227B, 227C and 227D. The charge storage unit FD forms an input unit of the amplification transistor 224 and is a floating diffusion capacitor which temporarily stores and accumulates signal charges transferred from the photoelectric conversion elements 221A, 221B, 221C and 221D.
The reset transistor 223 is a transistor which resets the charge storage unit FD. Turning-on and turning-off of the reset transistor 223 are controlled by a reset pulse supplied from the control circuit 209 via the reset line 228. The reset transistor 223 and the transfer transistors 222A, 222B, 222C and 222D are turned on together, and thereby the photoelectric conversion elements 221A, 221B, 221C and 221D can be reset.
The amplification transistor 224 is a transistor which outputs, from the source thereof, an amplified signal obtained by amplifying a signal which is input to the gate thereof, based on the signal charge accumulated in the charge storage unit FD. The activation transistor 225 and the injection transistor 230 are transistors which supply a current for driving the amplification transistor 224 to the amplification transistor 224. Turning-on and turning-off of the activation transistor 225 are controlled by an activation pulse supplied from the control circuit 209 via the activation line 229, and turning-on and turning-off of the injection transistor 230 are controlled by an injection pulse supplied from the control circuit 209 via the injection line 231.
A single pixel cell 207 collecting four pixel is constituted by the photoelectric conversion elements 221A, 221B, 221C and 221D, the transfer transistors 222A, 222B, 222C and 222D, the reset transistor 223, the amplification transistor 224, the activation transistor 225, and the injection transistor 230. In addition, in the related art, on the first substrate 201, there is no vertical signal line for outputting a signal which is read to an external device of the substrate.
Next, with reference to 15, an operation of the pixel cell 207 will be described. First, an injection pulse Pn1 is applied to the injection transistor 230 via the injection line 231 so as to be turned on, and the potential of the output terminal 226 is fixed to 0 V. Next, a reset pulse Pr is applied to the reset transistor 223 via the reset line 228 so as to be turned on, and the potential of the charge storage unit FD is reset to a high level (power supply potential). When the potential of the charge storage unit FD becomes a high level, the amplification transistor 224 is turned on. Next, after the application of the injection pulse Pn1 is stopped and thus the injection transistor 230 is turned off, an activation pulse Pk1 is applied to the activation transistor 225 via the activation line 229 so as to be turned on. The activation transistor 225 is turned on, and thereby the potential of the output terminal 226 increases to a potential corresponding to the potential of the charge storage unit FD. The potential of the output terminal 226 at this time is referred to as a reset level.
Next, after the application of the activation pulse Pk1 is stopped and thus the activation transistor 225 is turned off, a transfer pulse Pt1 is applied to the transfer transistor 222A via the transfer line 227A so as to be turned on, and thereby a signal charge of the corresponding photoelectric conversion element 221A is transferred to the charge storage unit FD. Next, an injection pulse Pn2 is applied to the injection transistor 230 via the injection line 231 so as to be turned on, and the potential of the output terminal 226 becomes 0 V. Thereafter, an activation pulse Pk2 is applied to the activation transistor 225 via the activation line 229 so as to be turned on, and thereby the potential of the output terminal 226 increases to a potential corresponding to the potential of the charge storage unit FD. The potential of the output terminal 226 at this time is referred to as a signal level.
A signal based on the potential of the output terminal 226 is input to the second substrate 202 via the micro bumps 205. A difference between the signal level and the reset level is detected in the second substrate 202, and, an analog signal corresponding to the difference is digitalized, is demultiplexed, is stored in a memory, and is then sequentially output from the solid-state image pickup device. Here, an operation of reading a signal of the photoelectric conversion element 221A of the four photoelectric conversion elements 221A, 221B, 221C and 221D has been described. The same operation is sequentially performed on the other three photoelectric conversion elements 221B, 221C and 221D.
Through the operation, there is a slight difference in photosensing timing between the photoelectric conversion elements 221A, 221B, 221C and 221D; however, the photosensing timing is substantially aligned in a screen, thus synchronization of exposure in the upper side and the lower side of the pixel unit 208 can be realized, and thereby image processing speed can be also improved without causing considerable deterioration in image quality when a signal is read.
In the above-described related art, there is a slight difference in photosensing timing between the four photoelectric conversion elements 221A, 221B, 221C and 221D; however, the photosensing timing is substantially aligned in a screen, and thus synchronization of exposure in the upper side and the lower side of the pixel unit 208 can be realized. In order to realize the synchronization of exposure, the solid-state image pickup device in the related art includes an AD conversion circuit which converts an analog signal output from pixels into a digital signal, and memories holding digital signals of the same number as that of the photoelectric conversion elements.
In an operation in a mode for displaying a live view image on a view finder, or in a mode for recording moving images for HDTV, it is expected that 60 or more frames per second are required, or 120 frames per second are required depending on the case. In order to read signals at a high frame rate from all the pixels using recent digital cameras with increased pixels, many reading circuits are required to be operated in parallel. However, it is very difficult to realize reading at a high frame rate due to an increase in chip area or an increase in power consumption.
On the other hand, in live view image display or an HDTV moving image mode, the number of pixels such as twelve million pixels or sixteen million pixels is not necessary. For this reason, when signals are read from the pixels, a method of reading signals by thinning out pixels is considered. However, if the thinning-out is performed, moiré fringes occur and thus image quality deteriorates.